1. Field of the Invention
Embodiments of the present invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to a flash memory device and an associated recharge method.
A claim of priority is made to Korean Patent Application No. 10-2005-0087635, filed on Sep. 21, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Flash memory is a popular form of non-volatile memory included in a wide variety consumer and industrial electronic devices such as cellular phones, personal computers, cameras, portable memory sticks, and personal digital assistants, to name but a few. Several aspects of flash memory make it a particularly attractive option for portable electronic devices. These aspects include its high degree of integration, high operating speed, low power consumption, and high resistance to physical shock. An example of a flash memory device is disclosed in Japanese Laid-open Patent Application No. 2003-178590.
A flash memory device typically comprises a plurality of memory cells divided into a plurality of memory blocks. The memory cells can be programmed or read in units of individual memory cells, bytes, or words, but the memory cells must be erased an entire memory block at a time.
Most flash memory devices can be broadly classified into one of two categories, depending on the arrangement of memory cells within the devices. The two categories include NAND-type flash memory devices, and NOR-type flash memory devices. In general, NAND-type flash memory devices have faster program and erase times, a lower cost per bit, and a higher degree of integration than NOR flash memory devices. On the other hand, NOR-type flash memories tend to have faster read times. As a result, NAND-type flash memories are generally preferred over NOR-type flash memories for use as mass data storage units.
The memory cells of a NAND-type flash memory device are organized in a plurality of strings, wherein each string comprises a plurality of memory cells connected in series between a source line and a bit line. Such a string of memory cells constitutes a memory block of the NAND-type flash memory device. Because the memory cells in each memory block of a NAND-type flash memory device are connected in series, the memory cells must be accessed sequentially.
NAND-type flash memories are commonly designed to have a memory mat (MAT) structure including a plurality of memory blocks. In general, a memory mat structure is an arrangement of memory components designed to emulate a variety of memory structures. A memory mat structure typically has a fixed access width corresponding to a word width of a system that includes the memory mat structure. In addition, a NAND-type flash memory device can aggregate several memory mats to provide a wider access width. For example, if the access width of a single memory mat is 8 bits, two memory mats can be aggregated to provide a 16 bit access width.
FIG. 1 is a schematic block diagram illustrating a flash memory device 100 including two memory mats. In other words, flash memory device 100 has a two-MAT structure.
Referring to FIG. 1, flash memory device 100 includes a first MAT 110 and a second MAT 120. A word line decoder 130 is disposed between first MAT 110 and second MAT 120, and memory blocks 111 and 121 are respectively arranged in first MAT 110 and second MAT 120.
A first pump circuit 112 and a second pump circuit 122 provide respective first and second high voltages VPP1 and VPP2 to first MAT 110 and second MAT 120 through word line decoder 130. The respective levels of first and second high voltages VPP1 and VPP2 can be either a program voltage Vpgm, an erase voltage Verase, a read voltage Vread, or a pass voltage Vpass, depending on an operating mode of flash memory device 100.
FIG. 2 is a circuit diagram illustrating an example of first pump circuit 112, word line decoder 130, and memory block 111 shown in FIG. 1. Referring to FIG. 2, memory block 111 comprises “n” memory strings CS respectively connected to “n” bit lines BL0 through BLn−1. Each of memory strings CS comprises a string select transistor SST connected to a corresponding bitline, a plurality of memory cells M0 through M15, and a ground selection transistor GST. String select transistor SST, memory cells M0 through M15, and ground selection transistor GST are connected in series between the corresponding bitline and a common select line CSL.
The gates of memory cells M0 through M15 within each of memory strings CS are respectively connected to word lines WL0 through WL15. The gates of string selection transistors SST connecting memory strings CS to the respective bit lines BL0 through BLn−1 are connected to a string selection line SSL. The gates of ground selection transistors GST connecting memory strings CS to common source line CSL are connected to a ground selection line GSL.
Word line decoder 130 selectively activates string selection line SSL, ground selection line GSL, and word lines WL0 through WL15 of memory block 111. Word line decoder 130 comprises a decoder 132 receiving address signals ADDR and generating word line driving signals S0 through S15. Word line decoder further comprises a string selection voltage VSSL, a ground selection voltage VGSL, and a word line driver 134 for transferring word line driving signals S0 through S15, string selection voltage VSSL, and ground selection voltage VGSL to word lines WL0 through WL15, string selection line SSL, and ground selection line GSL.
Decoder 132 decodes address signals ADDR, and provides corresponding driving voltages to string selection line SSL, word lines WL0 through WL15, and ground selection line GSL. For example, decoder 132 provides program voltage Vpgm, erase voltage Verase, read voltage Vread, and pass voltage Vpass to string selection line SSL, word lines WL0 through WL15, and ground selection line GSL in a program operation, an erase operation, and a read operation, respectively.
Word line driver 134 includes high voltage pass transistors SN, WN0 through WN15, GN, and CN, for respectively applying string selection voltage VSSL, word line driving signals S0 through S15, ground selection voltage VGSL, and common source line voltage VCSL, to string selection line SSL, word lines WL0 through WL15, ground selection line GSL, and common source line CSL. First high voltage VPP1 output from first pump circuit 112 is applied to a block word line BLKWL in which gates of high voltage pass transistors SN, WN0 through WN15, GN, and CN are connected to each other.
First pump circuit 112 generates first high voltage VPP1 by a charge pumping operation when a pumping clock signal is applied. First high voltage VPP1 generated by first pump circuit 112 is provided to block word line BLKWL.
In the program operation, program voltage Vpgm is applied to an enabled word line, for example, to a first word line WL0, and pass voltage Vpass is applied to remaining word lines WL1 through WL15. In order to drive first word line WL0 using program voltage Vpgm provided by decoder 132, program voltage Vpgm is applied as a word line driving signal S0, and first high voltage VPP1 is applied to block word line BLKWL, so that pass transistor WN0 is turned on.
Program voltage Vpgm increases in proportion to the number of programmings and is generally between 15 V and 20 V. In order to transfer program voltage Vpgm without a voltage drop, first high voltage VPP1 is higher than program voltage Vpgm by a threshold voltage Vth of high voltage pass transistor WN0.
FIG. 3 is a graph plotting first high voltage VPP1 and second high voltage VPP2 when flash memory device 100 operates.
Referring to FIG. 3, first high voltage VPP1 rises to 20V during an interval TA when a program operation is performed and falls to about 4.5 V during an interval TB when a read operation is performed. Thereafter, in an interval TC, when another program operation is performed, first pump circuit 112 performs a pumping operation to raise first high voltage VPP1 to about 20 V.
If the pumping operation is repeatedly performed, power consumption of flash memory device 100 increases. Furthermore, due to the repeated pumping operations, a noise characteristic of the flash memory device 100 deteriorates. Accordingly, the flash memory device 100 is not suitable to install in various devices such as mobile phones.